Designing network on-chip architectures in the nanoscale era

Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication.

• ISBN: 978-1-4398-3710-8
• Editorial: Chapman and Hall/CRC
• Encuadernacion: Cartoné
• Páginas: 503
• Fecha Publicación: 17/12/2010
• Nº Volúmenes: 1
• Idioma: Inglés